The present invention relates generally to a digital circuit design, and more specifically to a digital circuit design that uses a placement process and a routing process.
Using Hardware Description Language (HDL), a digital circuit can be first designed at an abstract level (i.e. Register Transfer Levelxe2x80x94RTL) in terms of its functionality and data flow. The functionality of the design is validated through simulation. A logic synthesis process then converts the RTL description to a gate-level netlist, which is a description of the circuit design in terms of gates and their connections. Using the gate-level netlist, a placement process generates a placed netlist, in which each of these gates is placed in a location on a chip floor. Based on the placed netlist, a routing process generates a physical layout by routing conducting lines to connect these gates. The physical layout for the digital circuit design can be finally fabricated onto a silicon chip.
Frequently, particular gate placement and connection patterns (or configurations) can cause signal integrity and reliability problems. For example, when two long conducting lines are closely arranged in parallel with each other, the parallel configuration can result in signals carried on one line interfering with the signals carried on the other nearby lines, and vice versa. This is the so called xe2x80x9ccrosstalkxe2x80x9d problem. Traditionally, signal integrity and reliability problems are analyzed in the post-routing stage because these problems can be accurately analyzed after routing is complete.
One traditional solution to the problems is to make corrections to the physical layout based on the post-routing analysis. Unfortunately, it is difficult to correct these problems by modifying the physical layout. Most corrections require more chip resources (extra routing or extra gates), and a correction to one problem may cause other problems.
Another traditional solution to the problems is to modify the routing process to generate a new physical layout. However, routing modification at the post-routing stage allows only limited changes and this technique may not be able to find a solution without requiring revision of the placement process. It may take several reiterations of: post-routing analysis, routing modification, and placement modification. Because the traditional solution involves re-routing (including global-re-routing and local-re-routing) and re-placement, it is time consuming and not cost effective.
There is, therefore, a need for a method and apparatus to form a physical layout for a circuit design,with improved time and cost efficiency.
There is another need for a method and apparatus to form a physical layout for a circuit design with improved signal integrity and reliability in the post-routing stage.
There is yet another need for a method and apparatus to form a physical layout for a circuit design, which eliminate or reduce signal integrity and reliability problems in the post-routing stage, thus eliminating or reducing the modifications in the re-placement process or re-routing process.
The present invention provides a method and apparatus to meet these needs.
To address the shortcomings of the prior art, the present invention provides a novel method to form a physical layout for a circuit design.
In a broad aspect, the present invention provides a method for forming a physical layout on a chip floor based on a netlist for a circuit design. The netlist includes a plurality of gates. The method comprises the steps of: (a) assigning each of the gates to a location on the chip floor; (b) estimating potential signal integrity and reliability problems based on the assigned gate locations on the chip floor; (c) modifying the netlist based: on the estimation of the signal integrity and reliability problems, if the estimation made in step (b) is not acceptable; and (d) re-assigning each of the gates in the modified netlist in a location on the chip floor.
The present invention also provides a corresponding apparatus for performing the steps in the method described above.